1. Field of the Invention
The present invention relates in general to programmable delay lines and in particular to a pulse stuffing circuit for supplying additional input pulses to a delay line as necessary to maintain the delay line at minimum operating temperature.
2. Description of Related Art
A tapped delay line consists of a set of logic gates connected in series so that an input signal applied to the first gate of the series passes through each gate in succession. The output of each gate constitutes a separate output tap of the delay line, with the input signal appearing at each tap in succession. A delay between the appearance of the input signal at any one tap and a next succeeding tap of the delay line is determined by the switching speed of the gate linking the two taps. When the delay line taps drive separate inputs of a multiplexer, the tapped delay line and the multiplexer together form a programmable delay line. Programming data supplied to a control input of the multiplexer tells the multiplexer to select one of the delay line taps and to deliver the signal appearing on the selected delay line tap as a multiplexer output signal. The delay provided by the programmable delay line, the delay between the delay line input and the multiplexer output, is a function of the number of intervening gates the input signal passes through on its way to the selected tap. In particular, the total delay is equal to the sum of delays of the intervening gates and the delay provided by the multiplexer.
It is desirable that the delay provided by the delay line be a constant, predictable value for each tap selection. One source of variation in delay is variation in the frequency of the input signal being delayed. On the leading edge of an input signal pulse, a delay line gate turns on and begins supplying an output pulse to the input of the next gate of the delay line. On the trailing edge of the input signal pulse the gate turns off, thereby terminating the output pulse supplied to the next gate. For CMOS and similar technologies, since the gate generates heat during state transitions, it generates less heat at lower input signal frequencies than at higher input signal frequencies because it transitions less frequently. The delay of each gate of the delay line is determined by the rate at which it can transition from one state to the other. As a gate cools it is able to transition between states more rapidly, thereby decreasing its delay. Thus as the input signal frequency decreases, the delay provided by each gate of the delay line decreases, thereby decreasing the total delay of the delay line.
Some prior art systems sense the temperature of an integrated circuit forming a delay line and control a heater attached to the integrated circuit so as to maintain the integrated circuit at a constant temperature. This method is expensive to implement and is slow to correct for rapid, small swings in temperature that result from abrupt changes in input signal frequency. Other prior art systems sense the switching speeds of representative gates formed on the same integrated circuit as the delay line. Such systems control the integrated circuit power supply level so as to maintain the switching speed of the representative gates constant despite changes in integrated circuit temperature. Since the gates of the delay line use the same power supply, the switching speeds of these gates are also held constant despite changes in their temperature. This method works well but is also expensive to implement.
What is needed is an effective and inexpensive system for eliminating variation in delay of a programmable delay circuit arising from variations in frequency of the signal being delayed.